An injection-locked picosecond pulse detector is implemented in 65-nm CMOS technology. An on-chip slot planar inverted cone antenna receives picosecond pulses with a center frequency of 77 GHz and feeds the signal to a low-noise amplifier. A three-stage injection-locked frequency divider is used to lock the output signal to the 9.6-GHz repetition rate with an effective locking range of 142 MHz and a timing jitter of 0.29 psrms.
A CMOS impulse detector with a center frequency of 77 GHz is presented to achieve low-jitter interchip wireless time transfer. A wireless time transfer test with two impulse detector chips demonstrates that a low-jitter 9.5-GHz clock is distributed among widely spaced nodes in a large-aperture array.
The impulse detector, which includes an on-chip slot PICA, is based on a three-stage divide-by-8 ILFD. It is shown that a three-stage divider has better input sensitivity than a single-stage divide-by-8 divider. The output of the receiver is locked to the input repetition rate with a rms jitter of 0.29 ps.
The injection-locked detector is utilized in a wireless time transfer setup to demonstrate its application in widely spaced synchronized distributed arrays. This fully integrated system consumes 42 mW from a 1.3-V supply and occupies a total area of 0.9 mm2, including the on-chip antenna and the pads.