A Fully Integrated Injection-Locked Picosecond Pulse Receiver for 0.29psrms-Jitter Wireless Clock Synchronization in 65nm CMOS

We reported a picosecond pulse receiver based on a three-stage divide-by-8 injection locked frequency divider. The receiver operates for pulses with center frequency of 77 GHz and locks its output to the 9.6-GHz repetition rate with an effective locking range of 142 MHz. This receiver, which consumes 42 mW dc power, is used to demonstrate wireless clock synchronization with a 0.29ps RMS timing jitter and indicates an estimated sensitivity of −65.5 dBm in detecting picosecond pulses.

Publications

B. Jamali and A. Babakhani, “A Fully Integrated Injection-Locked Picosecond Pulse Receiver for 0.29psrms-Jitter Wireless Clock Synchronization in 65nm CMOS,” in IEEE MTT-S Int. Microwave Symposium, Jun 2017.